Video data like television video is generally transmitted using interlaced fields; that is, each frame is divided into an odd field and an even field. During transmission, a transmitting end only transmits the odd field of the de-interlaced frame and the even field of the interpolated frame to a receiving end. Using interlaced transmission, the transmission data amount is reduced by one half at any given time point. However, video data received at the receiving end is an even field or an odd field but not a complete frame. De-interlacing is used to process these sequent odd and even fields to generate a complete frame to be displayed on a display.
An example shall be given with reference of FIG. 1 showing a block diagram of a conventional image processing circuit at an image receiving end. An image processing circuit 10 comprises a de-interlacing module 110 and a motion interpolation module 120. The image processing circuit 10 comprises a memory unit 112 and a de-interlacing unit 114. The memory unit 112 receives and stores fields fi including a current field fi_p, a previous field fi_p-1, and next previous field fi_p-2. The de-interlacing unit 114 generates a frame fr according to the current and previous fields fi_p and fi_p-1, or the previous and next previous fields fi_p-1 and fi_p-2 provided by the memory unit 112. The motion interpolation module 120 comprises a memory unit 122, a motion estimation unit 124, and a motion compensation unit 126. The memory unit 122 stores current and previous frames fr_p and fr_p-1 of the frames fr. The motion estimation module 124 performs algorithm on the current and previous frames fr_p and fr_p-1 to obtain a motion vector MV. The motion compensation unit 126 performs interpolation according to the motion vectors, and current and previous frames fr_p and fr_p-1 to obtain an interpolation frame fr_in.
The foregoing memory unit 112 and a memory unit 122 may not be included in the image processing circuit 10. The fields and the frames may be stored in a dynamic random access memory (DRAM), which is coupled to the image processing circuit 10. When the de-interlacing module 110 performs de-interlacing or when the motion interpolation module 120 performs motion interpolation, the fields are read from the DRAM.
However, in the conventional image processing circuit 10, to store respectively data used for de-interlacing and motion interpolation, it is necessary that the memory units 112 and 122 have at least memory capacities for storing three fields and two frames. As a result, the conventional image processing circuit 10 has a drawback of high memory costs due to large memory capacities and bandwidths required.